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| ICX082AL Diagonal 11mm (Type 2/3) CCD Image Sensor for EIA Black-and-White Video Cameras Description The ICX082AL is an interline CCD solid-state image sensor suitable for EIA black-and-white video cameras with a diagonal 11mm (Type 2/3) system. High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable chargestorage time. 20 pin DIP (Ceramic) Pin 1 2 Features * High sensitivity (+6dB compared with the ICX022BL) * Low smear (-20dB compared with the ICX022BL) * High resolution, Low dark current * Excellent antiblooming characteristics * Continuous variable-speed shutter V 12 3 Pin 11 H 40 Optical black position (Top View) Device Structure * Interline CCD image sensor * Image size: * Number of effective pixels: * Total number of pixels: * Chip size: * Unit cell size: * Optical black: * Number of dummy bits: * Substrate material: Diagonal 11mm (Type 2/3) 768 (H) x 494 (V) approx. 380K pixels 811 (H) x 508 (V) approx. 410K pixels 10.25mm (H) x 8.5mm (V) 11.6m (H) x 13.5m (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels Horizontal 22 Vertical 1 (even fields only) Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95935C99 ICX082AL Block Diagram and Pin Configuration (Top View) 1 VL GND 7 9 2 3 4 Note) 5 6 V4 V3 V2 SUB GND V1 VDD 10 VOUT 11 VGG 12 VSS 13 GND 14 Output Unit Vertical Register Horizontal Register 15 RD 16 RG 17 VL 18 H1 Note) 19 H2 : Photo sensor 20 HIS Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 V4 V3 V2 SUB GND V1 VL NC GND VDD GND Output amplifier drain power Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate (overflow drain) GND Vertical register transfer clock Protective transistor bias Pin No. Symbol 11 12 13 14 15 16 17 18 19 20 VOUT VGG VSS GND RD RG VL H1 H2 HIS Description Signal output Output amplifier gate bias Output amplifier source GND Reset drain Reset gate clock Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock Horizontal register input source bias -2- ICX082AL Absolute Maximum Ratings Item Substrate voltage SUB - GND HIS, VDD, RD, VOUT, VSS - GND Supply voltage HIS, VDD, RD, VOUT, VSS - SUB Vertical clock input pins - GND Vertical clock input voltage Vertical clock input pins - SUB Ratings -0.3 to +55 -0.3 to +20 -55 to +10 -15 to +20 to +10 to +15 to +17 -17 to +17 -10 to +15 -55 to +10 -65 to +0.3 -0.3 to +30 -0.3 to +24 -0.3 to +20 -30 to +80 -10 to +60 Unit V V V V V V V V V V V V V V C C 1 Remarks Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 - V4 H1, H2, RG, VGG - GND H1, H2, RG, VGG - SUB VL - SUB V1, V3, HIS, VDD, RD, VOUT - VL RG - VL V2, V4, VGG, VSS, H1, H2 - VL Storage temperature Operating temperature 1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%. Bias Conditions Item Output amplifier drain voltage Reset drain voltage Output amplifier gate voltage Output amplifier source Substrate voltage adjustment range Substrate voltage adjustment precision Reset gate clock voltage adjustment range Reset gate clock voltage adjustment precision Protective transistor bias Horizontal register input source bias Symbol VDD VRD VGG VSS VSUB VSUB VRGL VRGL VL VHIS 9 -3 0 -3 -11 14.7 -10.5 15.0 Min. 14.7 14.7 3.8 Typ. 15.0 15.0 4.2 Grounded with 750 resistor 19 +3 3.0 +3 -10 15.3 V % V % V V 3 VHIS = VDD 2 Max. 15.3 15.3 4.6 Unit V V V 5% 2 VRD = VDD Remarks -3- ICX082AL DC Characteristics Item Output amplifier drain current Input current Input current Symbol IDD IIN1 IIN2 Min. Typ. 6 1 10 Max. Unit mA A A 4 5 Remarks 2 Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. The adjustment precision is 3%. VSUB code -- one character indication VRGL code -- one character indication VRGL code VSUB code "Code" and optimal setting correspond to each other as follows. VRGL code 1 2 3 4 5 6 7 Optimal setting 0 VSUB code D 0.5 1.0 1.5 2.0 2.5 3.0 E f G h J K L m N P Q R S T U V W X Y Z Optimal setting 9.0 9.5 10.010.511.011.512.0 12.513.013.514.014.515.015.516.016.517.017.518.018.519.0 -4- ICX082AL Clock Voltage Conditions Item Readout clock voltage VVT VVH1, VVH2, VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage | VVH1 - VVH2 | VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage VH VHL VRG VRGL 6.0 -3.5 6.0 0 27.0 -0.5 -0.5 8.9 0.2 0 0 0.8 1.0 0.8 0.8 8.0 -3.0 13.0 3.0 32.0 Symbol Min. 14.5 -0.6 -9.6 Typ. 15.0 Max. 15.5 0 Unit V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 4 1 High-level coupling High-level coupling Low-level coupling Low-level coupling VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) Remarks Substrate clock voltage VSUB 1 The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Waveform diagram 3 3 Item Reset gate clock voltage Symbol VRGL VRG Min. -0.2 8.5 Typ. 0 9.0 Max. 0.2 9.5 Unit V V Remarks -5- ICX082AL Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Symbol CV1, CV3 CV2, CV4 CV12, CV34 Capacitance between vertical transfer clocks CV23, CV41 CV13 CV24 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor CH1, CH2 CHH CRG CSUB R1, R2, R3, R4 RGND RH Min. Typ. 2700 2700 2100 900 1000 500 47 58 7 800 22 3 10 Max. Unit Remarks pF pF pF pF pF pF pF pF pF pF V1 CV12 V2 R1 R2 RH H1 RH H2 CHH CV23 CV13 CH1 CH2 CV1 CV41 CV24 R4 CV2 CV4 RGND CV3 CV34 R3 V4 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit -6- ICX082AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M VVT 10% 0% M 2 tf 0V tr twh (2) Vertical transfer clock waveform V1 V3 VVH1 VVHH VVH VVHL VVHH VVHH VVHL VVHL VVH3 VVHH VVHL VVH VVL1 VVLH VVL3 VVLH VVLL VVL VVL VVLL V2 VVHH VVHH V4 VVHH VVHH VVH VVHL VVH VVH2 VVHL VVHL VVH4 VVHL VVL2 VVLH VVLH VVLL VVL VVL4 VVLL VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) -7- ICX082AL (3) Horizontal transfer clock waveform * Reset gate clock waveform tr twh tf 90% VH, VRG 10% VHL, VRGL twl (4) Substrate clock waveform 100% 90% M VSUB 10% 0% M 2 tf VSUB tr twh Clock Switching Characteristics Item Readout clock Symbol VT twh twl tr tf Unit s s Remarks During readout Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 62.6 1.3 20 5.38 5.38 11 13 51 0.74 62.1 20 0.5 0.1 0.1 15 0.01 0.01 2.0 0.5 19 0.5 0.1 0.1 15 0.01 0.01 2.0 0.5 19 Vertical transfer V1, V2 clock V3, V4 H Horizontal transfer clock H1 H2 Reset gate clock RG During s imaging ns During imaging s During parallel-serial s conversion ns s During drain charge Substrate clock SUB 1.5 1.8 -8- ICX082AL Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Dark signal Dark signal shading Flicker Lag Symbol S Vsat Sm SH Vdt Vdt F Lag Min. 500 800 0.0001 0.0003 25 2 1 5 0.5 Typ. 700 Max. Unit mV mV % % mV mV % % Measurement method 1 2 3 4 5 6 7 8 (Ta = 25C) Remarks Ta = 60C Ta = 60C Ta = 60C Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage and the reget gate clock voltage are set to the values indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [*A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity luminous intensity. 2) Standard imaging condition II : Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs x 250 [mV] 60 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of signal output, 350mV, measure the minimum value of the signal output. -9- ICX082AL 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 350mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 x x x 100 [%] (1/10V method conversion value) 10 350 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 350mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/350 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 350mV, and then measure the difference in the signal level between fields (Vf [mV]). Then substitute the value into the following formula. F = (Vf/350) x 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 350mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/350) x 100 [%] FLD V1 Light Strobe light timing Signal output 350mV Output Vlag (lag) - 10 - Drive Circuit 30V 15V 10k 56k 270k 0.01 15 1000P 33k 15 22k 3.3/35V 15k 3.3/ 35V XSUB -9V 22/20V 0.01 3.3/ 16V 27k 47k 15k 39k 5V XV1 XSG1 0.1 XV2 6 5 4 3 2200P 1M 17 20 18 19 2 1 10 9 8 7 CXD1268M VL V4 V3 V2 V1 NC SUB XV3 ICX082AL (BOTTOM VIEW) 91k 1/16V 100k 33k 100k HIS H2 H1 VL RG RD GND 20 10 10 19 18 17 16 15 14 13 750 100k 3.3/16V 100 10k VSS 12 VGG 11 3.3/ 16V 3.3/16V H2 0.1 H1 39k 0.1 RG 0.1 6V 0.1 74AC04 47k 0.1 100k 10/10V 3.3k VOUT -11V GND GND VDD - 11 - 15 16 1 3.3/25V 2 3 11 12 13 14 3.3/25V 0.01 4 5 6 7 8 9 10 XV4 XSG2 [A] CCD OUT 2.2/16V ICX082AL ICX082AL Spectral Sensitivity Characteristics (includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart V1 V2 Odd Field V3 V4 33.5 0.2 V1 V2 Even Field V3 V4 1.6 2.5 2.5 2.5 2.5 Unit : s - 12 - Drive Timing Chart (Vertical Sync) FLD VD BLK HD 10 520 15 20 265 525 1 2 3 4 5 - 13 - 246 135 246 13 5 494 493 V1 V2 V3 V4 135 246 CCD OUT 493 494 260 270 275 135 246 280 ICX082AL Drive Timing Chart (Horizontal Sync) HD BLK H1 1 2 3 5 40 10 30 20 22 1 2 3 1 2 3 10 20 H2 10 - 14 - RG V1 V2 V3 V4 SUB 760 768 1 2 3 5 20 ICX082AL ICX082AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks. - 15 - Package Outline Unit: mm 20pin DIP (800mil) 0 to 9 11 A D C 31.0 0.4 27.0 0.3 + 0.25 2-2.50 0 20 ~ ~ 2R3 .0 5.0 B + 0.15 2.00 0 (Reference Hole) 0.35 1. "A" is the center of the effective image sensor area. 2. A straight line "B" which passes through the centers of the reference hole and the elongated hole is the reference axis of vertical direction. 3. A straight line "C" which passes through the center of the reference hole at right angles to vertical reference line "B" is the reference axis of horizontal direction. 0.3 M 5.5 0.2 2.54 1.0 3.2 0.3 1Pin Index 0.46 1.27 4. The bottom "D" is the height reference. (Two points are specified.) 5. The center of the effective image area, specified relative to the reference hole is (H, V) = (13.15, 5.0) 0.15mm. 6. The angle of rotation relative to the reference line "B" is less than 1. 7. The height from the bottom "D" to the effective image area is 1.46 0.15mm. 8. Planar orientation of the effective image area relative to the bottom "D" is less than 60m. 9. The thickness of the cover glass is 0.75mm and the refractive index is 1.5. PACKAGE STRUCTURE PACKAGE MATERIAL Ceramic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY ICX082AL PACKAGE WEIGHT 5.9g 0.25 1 13.15 0.5 10 26.00 0.25 + 0.15 2.00 0 x 2.5 (Elongated Hole) (AT STAND OFF) H 20.2 0.3 V 20.32 26.0 - 16 - |
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